Logic Verification Engineer

Be a part of a logic verification team working on various logic verification tasks including direct testing,
random testing UVM based on SoC platforms as well as IP level. Verification includes both SW and HW verification tasks.
o Develop verification definitions for various products.
o Take part in overall chip level coverage based verification work
o Analyze and review product specifications for building related verification plans
o Act as a reviewer for other team members work
o Generate Behavioral Models for Analog blocks and verify it
o Write proper documentation for work being done
Position Qualifications
o BSc in Electrical Engineering, from a well-known university.
o 2 – 5 years of experience in full chip and block level logic verification
o Experienced and knowledgeable in advanced coverage based verification process using System Verilog and UVM – Advantage
o Experience in Verilog and System Verilog coding
o Assertions and other verification oriented features – advantage
o Candidate must possess passion and commitment for completing projects on time.