Verification Engineer

Responsibilities:
Investigate, invent, develop, innovate and improve challenging verification environments, from block-level to chip-level.
Working with sophisticated verification methodologies implementing System On Chip flows.
Close collaboration with the Design team, and supporting SW and Production teams.
Acquiring thorough knowledge and understanding of cutting edge industry technology and standards in various fields (communications, processors, interconnect, …).
 
Requirements:
B.Sc. in Electrical or Computer Engineering/Computer science from an established university
At least 3 years of experience in the Verification flow of complex designs from test plan definition to coverage closure
Experience in Specman – an advantage
Experience in UVM – an advantage
Background in System-On-Chip flows and on-chip interconnect protocols – an advantage
 
Personal skills:
Team player with proactive attitude
Thinker, self-learning, curious and motivated
Capable of understanding high level system flows and constraints