VLSI Verification

Senior VLSI verification engineer, 5+ years of relevant experience.
 
Responsibility:
Be a significant part in developing a complex and innovative SoC chip in early stage startup.
Design and implement unit/soc level verification environment and tests in System-Verilog UVM.
Develop and execute test and coverage plans.
Work closely with design and software teams.
 
Requirements:
B.Sc./M.Sc. degree in electrical/computer engineering from a leading university.
In-depth knowledge of function verification flows and process.
Experience in leading block/cluster verification from scratch.
Experience in verification of complex SoC and designs.
Experience with CPU subsystem, AXI, DMA, DDR, NOC is an advantage.
Experience in System Verilog UVM.
Experience in formal verification is an advantage .
 
Location: 
Caesarea(Main) or Tel-Aviv, Israel