Experienced verification engineer

position requirements-B.Sc. in Electrical engineering/Software engineering.-At least 5 years of experience in digital verification.-Deep understanding of verification tools and methodologies – A must.-At least 3 years of experience in UVM and system verilog – a must.-Experience working in Unix (linux) environment.-Experience in SOC verification – an advantage.-Experience in communications verification – an advantage.-Experience in digital design in Verilog – an advantage.