For an exciting well-funded start-up, we are looking for layout engineers.
You will develop high end ADC/DAC in an advanced process for optical communication.
Minimum Qualifications
Experience of 3+ years in sub micro process %283n up to 16n TSMC%29
This experience must include:
• Expertise in Cadence Layout tools
• TSMC FIN FET technology design
• Good understanding of schematic flow
• Team work
• Strong understanding of high speed low noise layout requirements
• Experience in tape-out procedures
Preferred Qualifications
• Highly motivated
• Learning abilities
• Good communication
• Experience in both Mentor and Cadence tools is an advantage
