Responsibilities:
- Practicing the full range of verification aspects
- Creating a verification environment from scratch %28drivers, monitors, coverage…%29
- VIP %28DDR/PCIe/AXI%29 integration
- Defining verification sequences via a complex control-flow constraint set
- System understanding of a full-stack product with strong HW-SW coupling
- Reference model integration
- Test plan definition
- Defining verification flows and creating the proper infrastructure to support it
Requirements:
- At least 5 years experience- MUST%21
- Ability to ramp up verification environments from scratch
- Experience with UVM, System Verilog
- Knowledge of Verification IPs and protocols %28PCIe, DDR, AXI%29
- Experience with Xilinx FPGA IPs- Advantage
- Good understanding of HW/SW interaction- Advantage
- Knowledge in C/C++/Python- Advantage
