RESPONSIBILITIES
To cover full-life-cycle including specification, design and validation of various modules in the PHY and MAC layers of our next generation chipsets and supporting the physical design team in High-Level Block closure.
More specifically responsibilities will include:
Specification/microarchitecture of IC features
Implementation and maintenance of features in RTL
Verification of features in RTL simulation
Support Design Verification team in the testing of features
Support Platform Integration and SW team in their use of the designed features
Support physical design team in P&R and power-sensitive designs
Gate-Level simulations
JOB QUALIFICATIONS
B.Sc. / higher degree in Electrical Engineering / Computer Engineering
At least 5 years of hands-on experience in one or more of the following ASIC area:
PHY / signal processing
MAC and Network
Excellent knowledge and experience in Micro-Architecture and implementation using Verilog/System Verilog
Solid work experience involving Synthesis & STA – an advantage
Experience with multi-clock domain designs – an advantage
Familiar with all front-end tools including lint, CDC and synthesis – an advantage
SKILLS
Good System understanding
Excellent communication skills
Fluent in written and spoken English
Open-minded team player
Ability to work in a fast moving and multicultural environment