Design Verification

This position is 100% hands on plus technically leading 2-3 team members and involves working in System Verilog / UVM environment implementing random based test bench using state of the art verification methodologies and tools.
 
Minimum Qualifications
BSc in Electrical Engineering/ Computer Science
5+ years of meaningful hand on Verification engineering experience
Strong technical skills
 
 
Preferred Qualifications
Experience in verification / UVM / System Verilog Tech lead experience – an advantage.
 
Education Requirements
 
Required: Bachelor’s, Electrical Engineering or equivalent experience