Ø Digital DFT Insertion flow.
Ø DFT specifications, architecture and methods
Ø ATPG patterns and compressions
Ø MBIST Insertion
Ø Debug of post Silicon failures root cause analysis.
Position Qualifications
Ø At least 5 years of experience of DFT, leading DFT efforts for complex chip designs
Ø Experience with DFT specifications, architecture and methods for designs
Ø Experience with DFT simulators and debugging tools
Ø Experience with design verification methodologies for validating DFT implementation in simulation pre-silicon
Ø Debug of post Silicon failures root cause analysis
Ø Experience with ATPG patterns debugging, compressed ATPG patterns and MBIST
Ø Experience with STA constraints development and analysis for DFT modes and SDF simulations
Ø Experience with design flows utilizing Unix, Linux and Verilog / System Verilog;
Ø Knowledge and experience of working with Synopsys and Mentor as DFT tool;
Ø Excellent knowledge of working with IPs DFT integration;
Ø Experience with Multi Voltage. Multi Corner experience would be a plus;
Ø Sound programming skills and knowledge in scripting languages;
Ø Capable of assisting in determining methods and procedures to use on new projects and new design;
Ø Very good English language skills.
