Responsibilities:
- Define and track detailed test plans for the different modules and top levels.
- Implement scalable test benches including checkers, reference models, coverage groups in System Verilog.
- Keep track of coverage metrics and bugs encountered and fixed.
- Implement self-testing directed and random tests.
- Ability to communicate clearly.
Minimum Qualification:
- 2+ years of System Verilog OVM/UVM DV experience.
- Knowledge of Python, Perl, shell scripting.
- Knowledge with assertions %28SVA%29 or others.
- Knowledge of digital FPGAs design flows.
- Familiar with Matlab language
Advantages:
- ASIC Design/Verification experience
- Experience and strong foundations in digital design and communications.
- Beamforming knowledge
Education & Experience:
- BSc/ MSc in Electrical Engineering
- 3 or more years of experience.
