Verification Engineer

 Own tasks of ASIC verification 
-Develop test environments in System Verilog 
-Create verification plans  
-Debug ASIC designs 
-Integrate unknit level environment for full chip 
-Participate in design reviews 
-Collaborate with your peers in the architecture, design and SW teams 
 
  -3+ years of experience in ASIC Verification 
-Experience in functional verification on block level 
-Knowledge of building verification plan 
-Good communication skills 
-Fast learner 
-Advantage: Specman, System Verilog , E, UVM specman, System Verilog , E, UVM