Verification Engineer

Job Description

· Responsible for planning %28architecture%29 and developing %28coding%29 all the necessary simulation environments for tests and debugging.

· The Simulation environments are used for the development of new RTL blocks, full chip integration, FPGA code, and to debug and resolve bugs that are discovered.

Job Requirements

· BSC in Electrical Engineering – from a well-known university

· At least 3 years of experience as a verification engineer

· Knowledge of Specman – an advantage.

· Knowledge of UVM – an advantage.