Minimum requirements:
BSc in Computer science/ Electrical engineering.
3+ years experience as VLSI front-end engineer.
Experience with Verilog design coding.
Experience in micro-architecture and design of complex SoC blocks.
Proffered requirements:
Experience with DMA / Soft processors
Experience with multi-clock domain designs
Experience solving CDC/ synthesis/STA issues
Experience working with FPGAs
Experience in System Verilog and UVM
Script knowledge (Python, TCL, Perl, etc.)
Experience with legacy code understanding, debugging and problems solving attitude
Good communication & teamwork skills
Thorough and accurate
